The present invention relates to a logic circuit of complementary metal oxide semiconductor type (to be referred to as CMOS hereinafter) and, more particularly, to an AND-OR circuit.
When a CMOS circuit is conventionally used to implement an AND-OR circuit of the synchronous type, a circuit as shown in FIG. 1 is used to decrease the number of circuit elements required. More specifically, an AND circuit TN1 comprises n-channel pulldown MOS transistors, one end of each being selectively connected to signal lines D1 to D4 while the other end of each is grounded through an n-channel pulldown MOS transistor Tr1. Logic signals A, A, B, B, C and C are selectively supplied to the gates of the n-channel MOS transistors so as to control their ON/OFF states. P-channel precharge MOS transistors Tr2 to Tr5 are connected between a power supply Vcc and the signal lines D1 to D4, respectively. A synchronizing signal .phi.1 is supplied to the gates of the p-channel MOS transistors Tr2 to Tr5 to control their ON/OFF states and to simultaneously precharge the signal lines D1 to D4. The precharged signal lines D1 to D4 are kept charged or discharged by the n-channel pulldown MOS transistors which are selectively turned ON/OFF by the logic signals A, A, B, B, C and C. Thus, the signal lines D1 to D4 are set at potentials DA1 to DA4 which correspond to the logical products of predetermined combinations of the input logic signals A, A, B, B, C and C. The signals or potentials DA1 to DA4 of the signal lines D1 to D4 are selectively supplied to the gates of n-channel MOS transistors constituting an OR circuit TN2 so as to control the ON/OFF states of these n-channel transistors. One end of each of the n-channel MOS transistors constituting the OR circuit TN2 is selectively connected to a signal line E1, E2 or E3, and the other end of each MOS transistor is commonly grounded through an n-channel pulldown MOS transistor Tr6 whose gate is connected to receive a synchronizing signal .phi.2. P-channel precharge MOS transistors Tr7 to Tr9 are connected between the power supply Vcc and the signal lines E1 to E3. The ON/OFF states of the p-channel transistors Tr7 to Tr9 are controlled by the synchronizing signal .phi.2 supplied to their gates. The signal lines E1 to E3 are charged or discharged in accordance with the ON/OFF states of the n-channel MOS transistors constituting the OR circuit TN2. Potentials E01 to E03 which correspond to the AND-OR values for the predetermined combinations of the input signals A, A, B, B, C and C are produced from these signal lines E1 to E3, respectively.
The mode of operation of the circuit of FIG. 1 will now be described with reference to the timing charts shown in FIGS. 2(a) to 2(e). When the synchronizing signal .phi.1 is shown in FIG. 2(a) is at a logic level "0", the n-channel MOS transistor Tr1 is turned OFF and the p-channel MOS transistors Tr2 to Tr5 are turned ON. The power supply voltage Vcc is supplied to the signal lines D1 to D4 through the p-channel MOS transistors Tr2 to Tr5, respectively to precharge the signal lines D1 to D4. When the synchronizing signal .phi.1 goes to a logic level "1", the n-channel MOS transistor Tr1 is turned ON while the p-channel MOS transistors Tr2 to Tr5 are turned OFF. When the input logic signals A, A, B, B, C and C are supplied to the gates of the n-channel MOS transistors while the signal .phi.1 is kept at a "0" logic level, these n-channel MOS transistors are selectively turned ON or OFF. If at least one transistor connected to one of the signal lines D1 to D4 is in the ON state, the charge on this signal line is discharged to logic level "0". On the other hand, if all the transistors connected to one of the signal lines D1 to D4 are in the OFF state, this signal line is held at the precharged potential (logic level "1"). Therefore, the logic signals DA1 to DA4 on the signal lines D1 to D4, respectively, are obtained as follows: "DA1=A.multidot.B.multidot.C", "DA2=A.multidot.B.multidot.C, "DA3=A.multidot.B.multidot.C", and "DA4=A.multidot.B.multidot.C". When the synchronizing signal .phi.2, shown in FIG. 2(b), is at a logic level "0", the p-channel MOS transistors Tr7 to Tr9 are turned ON. The power supply voltage Vcc is supplied to the signal lines, E1 to E3, through the p-channel MOS transistors Tr7 to Tr9, respectively, to precharge the signal lines E1 to E3. The signal lines D1 to D4 are selectively connected to the gates of the n-channel MOS transistors in the OR circuit TN2 so that the conduction states of these n-channel MOS transistors may be determined in accordance with the signals on the signal lines D1 to D4. If at least one of the n-channel MOS transistors in the OR circuit TN2, which are connected to the same signal line of the signal lines E1, E2 and E3, is in the ON state, the signal line is discharged to a logic level "0" when the synchronizing signal .phi.2 is set at a "1" level. If all of the transistors connected to the same signal line are in the OFF state, this signal line goes to a logic level "1". Therefore, logic signals E01, E02 and E03 of the signal lines E1, E2 and E3, respectively, are as follows: "E01=DA1+DA3+DA4", "E02=DA2+DA4", and E03=DA1+DA2+DA3". Therefore, the output logic signals E01, E02 and E03 for the input logic signals A, A, B, B, C, C become as follows:
E01=A.multidot.B.multidot.C+A.multidot.B.multidot.C+A.multidot.B.multidot.C PA1 E02=A.multidot.B.multidot.C+A.multidot.B.multidot.C PA1 E03=A.multidot.B.multidot.C+A.multidot.B.multidot.C+A.multidot.B.multidot.C
When the input logic signals A and C are at a logic level "1" and the input logic signal B is at a logic level "0" as shown in FIG. 2(c), all of the transistors, one end of each being connected to the signal line D3 are turned OFF. Therefore, the signal line D3 is held at the precharged level of "1". However, since at least one of the transistors which have one end commonly connected to one of the signal lines D1, D2 and D4 is turned ON, the charge on the signal lines D1, D2 and D4 is discharged through the n-channel MOS transistor Tr1. The potentials DA1, DA2 and DA4 of the signal lines D1, D2 and D4, respectively, are kept at a logic level "0", as shown in FIG. 2(d). The ON/OFF states of the n-channel MOS transistors of the OR circuit TN2, the gates of which are selectively connected to the signal lines D1 to D4, are controlled by the potentials DA1 to DA4. Since two transistors whose conduction states are controlled by the signal line D3 and which have one end connected to the respective signal lines E1 and E3 are in the ON state, the signal lines E1 and E3 are discharged to a logic level "0". Since all of the transistors connected to the signal line E2 are in the OFF state, the signal line E2 is held at the precharged level of "1", as shown in FIG. 2(e).
However, with the circuit of the configuration as described above, synchronizing signals having two different phases are required, and a circuit to generate such synchronizing signals is complex. Furthermore, after a plurality of logical products are obtained in response to the first synchronizing signal .phi.1, logical sums of these logical products are obtained at the timing of the second synchronizing signal .phi.2. For this reason, the operating speed is decreased.